CEWiT builds technology demonstrators from prototypes to test beds in alignment with the research and technology projects being undertaken by it. This is a very crucial step in the life of a technology– moving from the algorithm and simulation levels to a realization scenario. The test bed and the various components that form part of it are also opened or licensed to partners for use in their R&D activities. They also help academic institutions in conducting research on wireless topics.

After developing a 4G LTE-test-bed in CEWiT earler, which was focused mainly on the L1 and L2 layers, it is currently developing an end to end 5G-NR test-bed that covers the L1, L2, L3, and the core network aspects including the backhaul, front-haul etc. for both sub 6GHz frequency bands and mm wave frequency bands.

Overview of the LTE test bed

2080
CEWiT’s LTE Test Bed is a Cost Effective LTE technology demo platform to emulate LTE Lower layers in real-time.  It is an effective tool to understand the technology and experiment with the implementations. The test bed has LTE PHY, MAC (Medium Access Layer), RLC (Radio Link Control) and minimal PDCP implementations. It is a useful platform to larger research community, industry or educational institutions for collaborative research and study purposes. It constitutes of both hardware and software.

The hardware is an EVM (Evaluation Module) of Texas Instruments (TI) System-On-Chip (SoC). TI provides a custom made LTE Base station SoC, with many key elements designed to meet the needs of LTE cellular base stations.

Features of the Test Bed

  • Basic implementation of LTE L1 downlink and uplink chains
  • L2 MAC, RLC and a thin layer of PDCP
  • Both eNodeB and UE implementations
  • Baseband level interface between eNodeB and UE using HYPERLink Hi-speed cable
  • End-to-end IP application flow both in DL, UL and simultaneous DL & UL

Technical Specifications

Hardware:

  • Two EVMs are used for setup, one is for UE and another for eNodeB.
  • These two EVMs are connected through Hyperlink cable.
  • SoC used in EVM is TI’s TMS320TCI6614 Communications Infrastructure SoC.
  • SoC has following features
    • 4 DSP Cores, one ARM Core. Each DSP runs at 1.2GHz and ARM runs at 1.2GHz
  • Hardware accelerators for LTE PHY bit level processing, for DFT, for decoding convolutional encoded data and turbo encoded data.
  • Gigabit Ethernet for interfacing with application
  • Antenna Interface peripheral to transfer/receive analog IQ samples to/from RF device/card. It supports standard interfaces like CPRI and OBSAI
  • Hardware accelerators for LTE PHY bit level processing, for DFT, for decoding convolutional encoded data and turbo encoded data.
  • Gigabit Ethernet for interfacing with application
  • Antenna Interface peripheral to transfer/receive analog IQ samples to/from RF device/card. It supports standard interfaces like CPRI and OBSAI

Software

  • LTE PHY stacks for eNodeB and UE
    • Supports 3GPP Release 8 specifications
    • Supports up to 10 MHz bandwidth and can be extended to 20MHz
    • Uses hardware accelerators and DSP modules
  • LTE L2 (MAC,RLC,PDCP) for eNodeB and UE
    • Supports 3GPP Release 8 specifications
    • Full-fledged MAC , RLC available.
    • Inbuilt PHY abstractor to test end-to-end flow without PHY support

2081